1. Field of the Invention
This invention relates to divider circuits and more particularly to adjusting a phase of an output of the divider circuit.
2. Description of the Related Art
In high speed clock applications, it is common to try and adjust the output phase of the clock output of a divider circuit that divides a high frequency clock. A typical implementation tries to achieve a resolution of the phase adjustment that is one period of the high frequency clock input.
One approach to adjust the phase of the output clock of a divider is to temporarily change the divide ratio. The basic idea of phase adjustment of the output clock of a clock divider by temporarily changing the divide ratio is illustrated in the waveforms shown in FIGS. 1A and 1B. FIG. 1A shows a phase increment adjustment and FIG. 1B shows a phase decrement adjustment.
FIG. 2A is a block diagram of a divider circuit that performs a divide by N. The divider circuit 200 receives an input clock CLKIN and supplies an output clock CLKOUT. When a phase change is desired, the divide ratio is changed from N to N−1 or N+1 for one low frequency output clock (CLKOUT) period based on whether a phase decrement or an increment is desired. The divider circuit 200 receives phase adjust signals SC and SA that respectively cause the divider circuit 200 to change the divide ratio to N+1 and N−1 for one cycle of the output clock.
In the waveforms of FIGS. 1A and 1B, a divide by 4 is illustrated, i.e., N=4. In the example in FIG. 1A, the input clock CLKIN is normally divided by four so the output clock has four input clock periods for the output clock periods 100 and 102.
Referring to FIG. 2B, illustrated is a circuit generating a pulse SC used to cause a phase increment. Referring to FIGS. 1A and 2B, pulsing the INC input 205 results in a pulse on input SC 210 of the divider 200 for one period of the output clock CLKOUT. The one period 101 in FIG. 1 has N+1 input clock periods. That results in the rising edge of the next rising edge of output clock CLKOUT coming out one CLKIN period later.
A circuit causing a pulse used to cause a decrement pulse is shown in FIG. 2C. A pulse on DEC 207, indicating a desire to decrement the phase of the output signal, results in an output pulse on SA 212 being supplied to the divider 200. The resulting decrement operation is illustrated in FIG. 1B. Normally, the input clock CLKIN is divided by four to generate the output clock CLKOUT as shown at 110, 112, and 114. However, as a result of SA being asserted, the period of the output clock is shortened by one input clock period at 111. That causes the rising edge of the output clock CLKOUT to occur one input clock period earlier, thus adjusting its phase.
However, the brute force approach of changing the divide ratio directly for one cycle of the output clock does not work very well for high frequency applications. One issue is the difficulty in meeting timing requirements while changing the divide ratio. Other issues are glitching, higher power consumption, the complexity of implementation, and increased jitter in some cases.
Accordingly, it would be desirable to provide an improved approach to dividing high speed clock signals.